A43L8316 datasheet(36/45 Pages) AMICC

36 / 45 page

A43L8316

Preliminary (April, 2000, Version 1.0)

AMIC Technology, Inc.

High

CLOCK

CKE

RAS

CAS

ADDR

Row Active

(A-Bank)

: Don't care

RAa

A8/AP

CAa

RAa

QAb1

QAb0

DBc0

DQM

QAb1

QAb0

DBc0

QAd0

(CL=2)

QAd0

(CL=3)

Write with

Auto Precharge

(B-Bank)

Write

(A-Bank)

RAc

Row Active

(A-Bank)

DAa0

QAd1

DAa0

QAd1

* Note 2

RBb

CAb

CBc

CAd

RAc

RBb

Row Active

(B-Bank)

Read with

Auto Precharge

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Burst Read Single Bit Write Cycle @Burst Length=2, BRSW

* Note : 1. BRSW mode is enabled by setting BA “High” at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

The next cycle starts the precharge.

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