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STM8L151C8 데이터시트(PDF) 101 Page - STMicroelectronics |
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STM8L151C8 데이터시트(HTML) 101 Page - STMicroelectronics |
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101 / 134 page ![]() DocID17943 Rev 6 101/134 STM8L15xx8, STM8L15xR6 Electrical parameters 121 Figure 35. Typical NRST pull-up resistance RPU vs. VDD Figure 36. Typical NRST pull-up current Ipu vs. VDD The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 42. Otherwise the reset is not taken into account internally. For power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF. Figure 37. Recommended NRST pin configuration 0.1 F EXTERNAL RESET CIRCUIT STM8L RSTIN MS32619V1 |
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