PIC24FJ128GA310 datasheet(225/406 Pages) MICROCHIP

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 2010-2011 Microchip Technology Inc.

DS39996F-page 225

PIC24FJ128GA310 FAMILY

bit 1

SPITBF:

SPIx Transmit Buffer Full Status bit

= Transmit has not yet started, SPIxTXB is full

= Transmit has started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the SPIxTXB.

Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available

buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF:

SPIx Receive Buffer Full Status bit

= Receive is complete, SPIxRXB is full

= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last

unread buffer location. Automatically cleared in hardware when a buffer location is available for a trans-

fer from SPIxSR.

SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

Note 1:

If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4

“Peripheral Pin Select (PPS)”

for more information.

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