PIC24FJ128GA310 datasheet(41/406 Pages) MICROCHIP

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 2010-2011 Microchip Technology Inc.

DS39996F-page 41

PIC24FJ128GA310 FAMILY

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows direct

access of program memory from the data space during

code execution.

4.1

Program Memory Space

The program address memory space of the

PIC24FJ128GA310 family devices is 4M instructions.

The space is addressable by a 24-bit value derived

from either the 23-bit Program Counter (PC) during pro-

gram execution, or from table operation or data space

remapping, as described in Section 4.3 “Interfacing

Program and Data Memory Spaces”

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

Memory maps for the PIC24FJ128GA310 family of

devices are shown in Figure 4-1.

FIGURE 4-1:

PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES

000000h

0000FEh

000002h

000100h

F8000Eh

F80010h

FEFFFEh

FFFFFEh

000004h

000200h

0001FEh

000104h

Note:

Memory areas are not shown to scale.

FF0000h

F7FFFEh

F80000h

800000h

7FFFFEh

Reset Address

Device Config Registers

User Flash

Program Memory

(22K instructions)

DEVID (2)

GOTO

Instruction

Reserved

Alternate Vector Table

Reserved

Interrupt Vector Table

PIC24FJ64GA3XX

Reserved

Flash Config Words

Unimplemented

Read ‘0’

015800h

0157FEh

00AC00h

00ABFEh

Reset Address

DEVID (2)

GOTO

Instruction

Reserved

Alternate Vector Table

Reserved

Interrupt Vector Table

PIC24F128GA3XX

Flash Config Words

Device Config Registers

Reserved

Unimplemented

Read ‘0’

User Flash

Program Memory

(44K instructions)

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