PIC24FJ128GA310 datasheet(346/406 Pages) MICROCHIP

346 / 406 page

PIC24FJ128GA310 FAMILY

DS39996F-page 346

 2010-2011 Microchip Technology Inc.

29.4.3

CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

inadvertent or unwanted changes or reads in two ways.

The primary protection method is the same as that of

the RP registers – shadow registers contain a compli-

mentary value which is constantly compared with the

actual value.

To safeguard against unpredictable events, Configura-

tion bit changes resulting from individual cell level

disruptions (such as ESD events) will cause a parity

error and trigger a device Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the GCP bit is set, the source data for device

configuration is also protected as a consequence. Even

if General Segment protection is not enabled, the

device configuration can be protected by using the

appropriate code segment protection setting.

29.5

JTAG Interface

PIC24FJ128GA310 family devices implement a JTAG

interface, which supports boundary scan device

testing.

29.6

In-Circuit Serial Programming

PIC24FJ128GA310 family microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock (PGECx)

and data (PGEDx), and three other lines for power

(VDD), ground (VSS) and MCLR. This allows customers

to manufacture boards with unprogrammed devices

and then program the microcontroller just before

shipping the product. This also allows the most recent

firmware or a custom firmware to be programmed.

29.7

In-Circuit Debugger

When MPLAB® ICD 3 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the PGECx (Emulation/Debug Clock) and

PGEDx (Emulation/Debug Data) pins.

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS and the PGECx/PGEDx pin pair des-

ignated by the ICS Configuration bits. In addition, when

the feature is enabled, some of the resources are not

available for general use. These resources include the

first 80 bytes of data RAM and two I/O pins.

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