PIC24FJ128GA310 datasheet(163/406 Pages) MICROCHIP

163 / 406 page

 2010-2011 Microchip Technology Inc.

DS39996F-page 163

PIC24FJ128GA310 FAMILY

DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)

U-0

R/W-0, HS

—

—DSINT0

bit 15

bit 8

R/W-0, HS

U-0

R/W-0, HS

U-0

DSFLT

—

DSWDT

DSRTCC

DSMCLR

—

bit 7

bit 0

Legend:

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented:

Read as ‘0’

bit 8

DSINT0:

Interrupt-on-Change bit

= Interrupt-on-change was asserted during Deep Sleep

= Interrupt-on-change was not asserted during Deep Sleep

bit 7

DSFLT:

Deep Sleep Fault Detected bit

= A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been

corrupted

= No Fault was detected during Deep Sleep

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

DSWDT:

Deep Sleep Watchdog Timer Time-out bit

= The Deep Sleep Watchdog Timer timed out during Deep Sleep

= The Deep Sleep Watchdog Timer did not time out during Deep Sleep

bit 3

DSRTCC:

Real-Time Clock and Calendar Alarm bit

= The Real-Time Clock and Calendar triggered an alarm during Deep Sleep

= The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep

bit 2

DSMCLR:

MCLR Event bit

= The MCLR pin was active and was asserted during Deep Sleep

= The MCLR pin was not active, or was active, but not asserted during Deep Sleep

bit 1-0

Unimplemented:

Read as ‘0’

Note 1:

All register bits are cleared when the DSEN (DSCON<15>) bit is set.

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