AD120 datasheet(4/13 Pages) AMICC

4 / 13 page

AD120

PRELIMINARY

(August, 2001, Version 0.0)

AMIC Technology, Inc

Input/Output Pin Function

Pin No.

Symbol

I/O

Description

Clock pulse

R /L

Right / left direction control for shift register

When

R /L is LOW, data are shifted to the right, or ST1 / ST2

output0

output1

.…

output257.

When R /L is HIGH, data are shifted to the left, or ST1X / ST2X

output257

output256

...

output0.

XON

XON to force all the outputs to VH voltage.

It is not synchronous to CP.

XOFF

XOFF to force all the outputs to VOFF voltage.

It is not synchronous to CP.

OGW

Output Gate pulse Width to select output_waveform format.

4,5,

13,14

ST1, ST2,

ST1X, ST2X

I/O

When

R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined

as outputs .

The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses.

When

R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined

as outputs.

The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses.

18 - 275

OUT0~

OUT257

Output drivers

These outputs are synchronized to CP pulses.

The output format and voltage level are controlled by OGW, XON, XOFF , ST1 /

ST2, ST1X / ST2X and

R /L correspondingly as shown in the diagram.

VSS

PWR

Reference voltage

VDD

PWR

Supply voltage for logic operation

VDD and VSS are voltage levels of input / output logic signals

3, 15

PWR

High voltage for output drivers

1, 17

PWR

Low voltage for output drivers

2, 16

VOFF

PWR

OFF voltage for output drivers

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