STM32F217VG datasheet(99/173 Pages) STMICROELECTRONICS

99 / 173 page

STM32F21xxx

Electrical characteristics

Doc ID 17050 Rev 8

99/173

5.3.17

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 43).

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 11.

Figure 36.

Recommended NRST pin

protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 46. Otherwise the reset is not taken into account by the device.

Table 46.

NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST)

(1)

NRST input low level voltage

TTL ports

2.7 V

≤ VDD ≤ 3.6 V

VSS−0.3

0.8

VIH(NRST)

(1)

NRST input high level voltage

VDD+0.3

VIL(NRST)

(1)

NRST input low level voltage

CMOS ports

1.8 V

≤ VDD ≤ 3.6 V

VSS−0.3

0.3VDD

VIH(NRST)

(1)

NRST input high level voltage

0.7VDD

-VDD+0.3

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

RPU

Weak pull-up equivalent resistor(2)

VIN = VSS

VF(NRST)

(1)

NRST Input filtered pulse

100

VNF(NRST)

(1)

NRST Input not filtered pulse

VDD > 2.7 V

300

TNRST_OUT

Generated reset pulse duration

Internal Reset source

µs

Guaranteed by design, not tested in production.

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance must be minimum

(~10% order)

ai14132c

STM32Fxxx

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit(1)

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