74LVC2G00

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Product data sheet

Rev. 12 — 8 April 2013

3 of 20

NXP Semiconductors

74LVC2G00

Dual 2-input NAND gate

5.

Functional diagram

6.

Pinning information

6.1 Pinning

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

001aah748

1A

1B

1Y

2A

2B

2Y

001aah749

&

&

mna099

B

A

Y

Fig 4.

Pin configuration SOT505-2 and SOT765-1

Fig 5.

Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203

74LVC2G00

1A

1B

1Y

2Y

2B

GND

2A

001aab736

1

2

3

4

6

5

8

7

74LVC2G00

2B

1Y

2A

2Y

1B

1A

GND

001aab737

36

27

18

45

Transparent top view

Fig 6.

Pin configuration SOT996-2

Fig 7.

Pin configuration SOT902-2

001aai251

74LVC2G00

Transparent top view

8

7

6

5

1

2

3

4

1A

1B

2Y

GND

1Y

2B

2A

001aae980

1B

2B

1A

2Y

1Y

2A

Transparent top view

3

6

1

5

7

2

terminal 1

index area

74LVC2G00