DSP56374 datasheet(33/64 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

Figure 3. Reset Timing

Interrupt Requests Rate1

• ESAI, ESAI_1, SHI, Timer

12 x TC

—80.0

•DMA

8 x TC

—53.0

•IRQ, NMI (edge trigger)

8 x TC

—53.0

•IRQ (level trigger)

12 x TC

—80.0

DMA Requests Rate

• Data read from ESAI, ESAI_1, SHI

6 x TC

—40.0

• Data write to ESAI, ESAI_1, SHI

7 x TC

—46.7

• Timer

2 x TC

—13.4

•IRQ, NMI (edge trigger)

3 x TC

—20.0

Note:

1 When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through

21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is

recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2 For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will

be defined by the OMR Bit 6 settings.

For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop

requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range

of 0.5 ms.

3 Periodically sampled and not 100% tested.

4 RESET duration is measured during the time in which RESET is asserted, V

DD is valid, and the EXTAL input is

active and valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified

above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant

power consumption and heat-up. Designs should minimize this state to the shortest possible duration.

Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min

Max

Unit

VIH

RESET

Reset Value

All Pins

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