IO96NDB2V1 datasheet(148/242 Pages) MICROSEMI

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ProASIC3L DC and Switching Characteristics

2-132

Revision 13

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-212 • ProASIC3L CCC/PLL Specification

CCC/PLL Operating at 1.2 V

Parameter

Min.

Typ.

Max.

Units

Clock Conditioning Circuitry Input Frequency fIN_CCC

1.5

250

MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC

0.75

250

MHz

Delay Increments in Programmable Delay Blocks 1, 2

2703

Number of Programmable Values in Each Programmable Delay Block

Serial Clock (SCLK) for Dynamic PLL4

100

MHz

Input Cycle-to-Cycle Jitter (peak magnitude)

CCC Output Peak-to-Peak Period Jitter FCCC_OUT

Max Peak-to-Peak Period Jitter

1 Global

Network

Used

External

FB Used

3 Global

Networks

Used

0.75 MHz to 24 MHz

0.50%

0.75%

0.70%

24 MHz to 100 MHz

1.00%

1.50%

1.20%

100 MHz to 250 MHz

2.50%

3.75%

2.75%

Acquisition Time

LockControl = 0

300

µs

LockControl = 1

6.0

Tracking Jitter5

LockControl = 0

LockControl = 1

Output Duty Cycle

48.5

51.5

Delay Range in Block: Programmable Delay 1 1, 2

1.2

15.65

Delay Range in Block: Programmable Delay 2 1, 2

0.025

15.65

Delay Range in Block: Fixed Delay 1, 2

3.1

Notes:

1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings.

2. TJ = 25°C, VCC = 1.2 V

3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help for more information.

4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.

Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

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