EP2C8A datasheet(45/168 Pages) ALTERA

45 / 168 page

Altera Corporation

2–33

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Embedded multipliers can operate at up to 250 MHz (for the fastest speed

grade) for 18 × 18 and 9 × 9 multiplications when using both input and

output registers.

Each Cyclone II device has one to three columns of embedded multipliers

that efficiently implement multiplication functions. An embedded

multiplier spans the height of one LAB row. Table 2–10 shows the number

of embedded multipliers in each Cyclone II device and the multipliers

that can be implemented.

The embedded multiplier consists of the following elements:

■

Multiplier block

■

Input and output registers

■

Input and output interfaces

Figure 2–18 shows the multiplier block architecture.

Table 2–10. Number of Embedded Multipliers in Cyclone II Devices

Note (1)

Device

Embedded

Multiplier Columns

Embedded

Multipliers

9 × 9 Multipliers

18 × 18 Multipliers

EP2C5

EP2C8

EP2C15

EP2C20

EP2C35

EP2C50

172

EP2C70

150

300

150

Note to Table 2–10:

(1)

Each device has either the number of 9 × 9-, or 18 × 18-bit multipliers shown. The total number of multipliers for

each device is not the sum of all the multipliers.

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