PIC18F25852680 datasheet(31/482 Pages) MICROCHIP

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Preliminary

DS39625C-page 29

PIC18F2585/2680/4585/4680

2.7.1

OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in full

power operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC3:FOSC0 Configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator block. The clock source changes

immediately after one or more of the bits is written to,

following a brief clock transition interval. The SCS bits

are cleared on all forms of Reset.

The

Internal

Oscillator

Frequency

Select

bits,

IRCF2:IRCF0, select the frequency output of the

internal oscillator block to drive the device clock. The

choices are the INTRC source, the INTOSC source

(8 MHz) or one of the frequencies derived from the

INTOSC postscaler (31 kHz to 4 MHz). If the internal

oscillator block is supplying the device clock, changing

the states of these bits will have an immediate change

on the internal oscillator’s output. On device Resets,

the default output frequency of the internal oscillator

block is set at 1 MHz.

When an output frequency of 31 kHz is selected

(IRCF2:IRCF0 = 000), users may choose which

internal oscillator acts as the source. This is done with

the

INTSRC

bit

the

OSCTUNE

(OSCTUNE<7>). Setting this bit selects INTOSC as a

31.25 kHz clock source by enabling the divide-by-256

output of the INTOSC postscaler. Clearing INTSRC

selects INTRC (nominally 31 kHz) as the clock source.

This option allows users to select the tunable and more

precise INTOSC as a clock source, while maintaining

power savings with a very low clock speed. Regardless

of the setting of INTSRC, INTRC always remains the

clock source for features such as the Watchdog Timer

and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock

source is currently providing the device clock. The

OSTS bit indicates that the Oscillator Start-up Timer

has timed out and the primary clock is providing the

device clock in primary clock modes. The IOFS bit

indicates when the internal oscillator block has

stabilized and is providing the device clock in RC Clock

modes. The T1RUN bit (T1CON<6>) indicates when

the Timer1 oscillator is providing the device clock in

secondary clock modes. In power managed modes,

only one of these three bits will be set at any time. If

none of these bits are set, the INTRC is providing the

clock or the internal oscillator block has just started and

is not yet stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power Managed Modes”.

2.7.2

OSCILLATOR TRANSITIONS

PIC18F2585/2680/4585/4680 devices contain circuitry

to prevent clock “glitches” when switching between

clock sources. A short pause in the device clock occurs

during the clock switch. The length of this pause is the

sum of two cycles of the old clock source and three to

four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP

instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction, or a very

long delay may occur while the Timer1

oscillator starts.

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