SPC5601PEF0MLL4R datasheet(19/95 Pages) FREESCALE

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MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

1.5.30

IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.

The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

•

Selectable modes of operation include JTAGC/debug or normal system operation.

•

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

•

5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

•

3 test data registers:

— Bypass register

— Boundary scan register (size parameterized to support a variety of boundary scan chain lengths)

— Device identification register

•

TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

1.5.31

On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

•

Uses external NPN (negative-positive-negative) transistor

•

Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

•

Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

Package pinouts and signal descriptions

2.1

Package pinouts

The LQFP pinouts are shown in the following figures. For pin signal descriptions, please refer to Table 5.

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