AT89LS8252

4-143

Dual Data Pointer Registers To facilitate accessing both

internal EEPROM and external data memory, two banks of

16 bit Data Pointer Registers are provided: DP0 at SFR

address locations 82H-83H and DP1 at 84H-85H. Bit DPS

= 0 in SFR WMCON selects DP0 and DPS = 1 selects

DP1. The user should always initialize the DPS bit to the

appropriate value before accessing the respective Data

Pointer Register.

Power Off Flag The Power Off Flag (POF) is located at

bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during

power up. It can be set and reset under software control

and is not affected by RESET.

Table 3. WMCON—Watchdog and Memory Control Register

WMCON Address = 96H

Reset Value = 0000 0010B

PS2

PS1

PS0

EEMWE

EEMEN

DPS

WDTRST

WDTEN

Bit

7

6

54321

0

Symbol

Function

PS2

PS1

PS0

Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal

period of 16 ms. When all three bits are set to “1”, the nominal period is 2048 ms.

EEMWE

EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM

with the MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.

EEMEN

Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip

EEPROM instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data

memory.

DPS

Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1

selects the second bank, DP1

WDTRST

RDY/BSY

Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a

pulse is generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the

next instruction cycle. The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-

Only mode during EEPROM write. RDY/BSY = 1 means that the EEPROM is ready to be programmed.

While programming operations are being executed, the RDY/BSY bit equals “0” and is automatically reset to

“1” when programming is completed.

WDTEN

Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the

watchdog timer.