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Features

Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 pins

– 7 ns Maximum Pin-to-Pin Delay

– Registered Operation Up To 100 MHz

– Enhanced Routing Resources

– D/T/Latch Configurable Flip Flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic utilization by burying a register within a COM output

– Automatic 100

µµµµA Stand-By for “Z” Version

– Pin-Controlled 4 mA Stand-By Mode (Typical)

– Programmable Pin-Keeper Inputs and I/Os

– Reduced-Power Feature Per Macrocell

– 100% Tested

– Completely Reprogrammable

– 100 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-Up Immunity

Enhanced Features

– Edge Controlled Power Down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Description

The ATF1504AS is a high performance, high density Complex Programmable Logic

Device (CPLD) which utilizes Atmel’s proven electrically erasable memory technology.

With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several

High-

Performance

EE CPLD

ATF1504AS

ATF1504ASZ

Rev. 0950D–07/98

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