MCP23009TESS datasheet(27/50 Pages) MICROCHIP

27 / 50 page

DS22121B-page 27

MCP23009/MCP23S09

1.7

Interrupt Logic

If enabled, the MCP23X09 activates the INT interrupt

output when one of the port pins changes state or when

a pin does not match the pre-configured default. Each

pin is individually configurable as follows:

• Enable/disable interrupt via GPINTEN

• Can interrupt on either pin change or change from

default as configured in DEFVAL

Both conditions are referred to as Interrupt on Change

(IOC).

The Interrupt Control Module uses the following

registers/bits:

• GPINTEN - Interrupt enable register

• INTCON - Controls the source for the IOC

• DEFVAL - Contains the register default for IOC

operation

• IOCON (ODR and INTPOL) - configures the INT

pin as push-pull, open-drain, and active level

(high or low).

1.7.1

IOC FROM PIN CHANGE

If enabled, the MCP23X09 will generate an interrupt if

a mismatch condition exists between the current port

value and the previous port value. Only IOC enabled

pins will be compared. See GPINTEN and INTCON

registers.

1.7.2

IOC FROM REGISTER DEFAULT

If enabled, the MCP23X09 will generate an interrupt if

a mismatch occurs between the DEFVAL register and

the port. Only IOC enabled pins will be compared. See

GPINTEN, INTCON, and DEFVAL registers.

1.7.3

INTERRUPT OPERATION

The INT interrupt output can be configured as “active

low”, “active high”, or “open-drain” via the IOCON

Only those pins that are configured as an input (IODIR

with

interrupt-on-change

(IOC)

enabled

(GPINTEN register) can cause an interrupt. Pins

configured as an output have no effect on the interrupt

output pin.

Input change activity on a port input pin that is enabled

for IOC will generate an internal device interrupt and

the device will capture the value of the port and copy it

into INTCAP.

The first interrupt event will cause the port contents to

be copied into the INTCAP register. Subsequent

interrupt conditions on the port will not cause an

interrupt to occur as long as the interrupt is not cleared

by a read of INTCAP or GPIO.

1.7.4

CLEARING INTERRUPTS

The interrupt will remain active until the INTCAP or

GPIO register is read (depending on IOCON.INTCC).

Writing to these registers will not affect the interrupt.

The interrupt condition will be cleared after the LSb of

the data is clocked out during a Read operation of

GPIO or INTCAP (depending on IOCON.INTCC).

Note:

Assuming IOCON.INTCC = 0 (INT cleared

on GPIO read): The value in INTCAP can

be lost if GPIO is read before INTCAP

while another IOC is pending. After read-

ing GPIO, the interrupt will clear and then

set due to the pending IOC, causing the

INTCAP register to update.

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