TS68C429AVF datasheet(18/43 Pages) ATMEL

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TS68C429A

2120A–HIREL–08/02

The lowest value will give the highest priority. If two channels have the same priority,

one of them will never be able to send its interrupt vector to the microprocessor. Each

channel must have a unique channel priority order.

Figure 11.

15 14 13 12 11 10 9876 54321

Channel enable

Test mode

Label control

Label control matrix write enable

Parity control

Not used

Wrong parity

Not used

Channel priority order

USD access

LDS access

Table 9. Register Control Register Description

Bit

Function

Comments

Bit 15

Channel enable

0: channel is out of service

1: channel is in service

Bit 14

Test mode

0: external ARINC lines as input (normal operation)

1: third transmitter lines as input (test mode)

Bit 13

Label control

0: no control, all the labels are accepted

1: automatic check of the label according to the label control matrix

Bit 12

LCMWE label control matrix

write enable

0: receiving mode (write to the matrix are disabled)

1: programmation mode for labels control matrix

Bit 11

Parity control

0: even parity check

1: odd parity check

Bit 10

Parity control

0: parity check is disable

1: parity check is enable

Bit 9

Not used

Bit 8

Not used

Bit 7

Wrong parity: this feature is

enabled only if the self-test

0: received message parity is correct if read, reset wrong wrong parity flag if written.

1: an incorrect received message parity has been detected (the corresponding

message is lost) (set by hardware).

Bit 6

Not used

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