FG256 datasheet(39/108 Pages) ACTEL

39 / 108 page

SX-A Family FPGAs

v5.3

2-19

tINYH

Input Data Pad to Y High 5 V PCI

0.5

0.6

0.7

0.9

tINYL

Input Data Pad to Y Low 5 V PCI

0.8

0.9

1.1

1.5

tINYH

Input Data Pad to Y High 5 V TTL

0.5

0.6

0.7

0.9

tINYL

Input Data Pad to Y Low 5 V TTL

0.8

0.9

1.1

1.5

Input Module Predicted Routing Delays2

tIRD1

FO = 1 Routing Delay

0.3

0.4

0.6

tIRD2

FO = 2 Routing Delay

0.5

0.6

0.8

tIRD3

FO = 3 Routing Delay

0.6

0.7

0.8

1.1

tIRD4

FO = 4 Routing Delay

0.8

0.9

1.4

tIRD8

FO = 8 Routing Delay

1.4

1.5

1.8

2.5

tIRD12

FO = 12 Routing Delay

2.2

2.6

3.6

Table 2-14 • A54SX08A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)

Parameter

Description

–2 Speed

–1 Speed

Std. Speed

–F Speed

Units

Min. Max. Min. Max.

Min.

Max.

Min. Max.

Notes:

1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

FG256 데이터시트(PDF) 39 Page - Actel Corporation

FG256 데이터시트(HTML) 39 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL