Pin A ssignment

A DC541

NOTES

1. Initial offset and gain errors are externally adjustable. See A PPLI-

CA TIONS INFORM A TION.

2. Includes effects of Linearity, offset, and gain errors.

A DC542

CA SE A (CERA M IC): A DC542

CA SE B (M ETA L): A DC541

0.165

(4.191)

0.010

(0.254)

0.600

(15.24)

0.018

(0.451)

0.100

(2.54)

1.295

(32.893)

0.790

(20.066)

0.025

(0.635)

0.205

(5.207)

TY PICA L

DIM ENSIONS

TOP

V IEW

PIN (1)

INDEX

12

13

1

24

0.010

(0.254)

0.600

(15.24)

0.775

(16.685)

0.018 ± 0.002

(0.045 ± 0.054)

inch

mm

M A X

DIM ENSION

inches

(mm)

0.220

(5.588)

M IN

0.175

(4.45)

M A X

1.275

(32.305)

M A X

0.100

(2.450)

TY P

0.10

(2.54)

0.03

(0.762)

STA NDOFFS

SUPPLIED

RED DOT

INDICA TES PIN 1

1

24

12

13

TOP V IEW

O RD ERIN G IN FO RMATIO N

M ODEL

DESCRIPTION

A DC541C-8

Commercial/Industrial Process

A DC541B-8

M IL-STD-883 Rev. C, Level B Process;

A DC542C-8

Commercial/Industrial Process

A DC82 Pin Out Compat.

A DC542B-8

M IL-STD-883 Rev. C, Level B Process;

A DC82 Pin Out Compat.

Specifications subject to change without notice.

SPECIFICATIO N S

(Typical @ +25ºC and nominal power supplies unless otherwise noted)

SERIES

A DC541/542

RESOLUTION

8-Bits

TY PE

Successive A pproximation

A NA LOG INPUT

Unipolar

0 to +5V , 0 to +10V . 0 to +20V

Bipolar

±2.5V , ±5V . ±10V

Impedance

500 /V olt

DIGITA L INPUTS

Start Command Pulse Input

100nS wide, min

Logic " 1" > +2.0V ;

Logic " 0" < +0.8

Logic Loading

2 TTL Loads

Clock in (A DC542 only)

2 TTL Loads

DIGITA L OUTPUTS

Data Coding, A DC541

Parallel Outputs Only

Unipolar

Binary

Bipolar

2‘s Complimentary Offset Binary

Data Coding, A DC542

Parallel and Serial Output

Unipolar

Complimentary Binary

Bipolar

Complimentary Offset Binary

Complimentary 2's Complement

Data Output Drive Capability

3TTL Loads

Logic " 1" > +2.4V

Logic " 0" > 0.4V

Status Output Drive Capability

2 TTL Loads,

Logic “ 1” during conversion

Clock Out (A DC542 only)

Frequency

2.85 M Hz

REFERENCE

Internal

CONV ERSION TIM E/

THROUGHPUT RA TE

2.5µS, typ; 2.8µS max/400 kHz

A CCURA CY

Quantization

±1/2 LSB max

Linearity

±0.2% of F.S.R. max

Offset,

Unipolar and Bipolar1

±0.2% of F.S.R. max

Gain1

±0.2% of F.S.R. max

STA BILITY

Over Specified Temperature Range

Linearity

±10ppm/ºC

Gain

±40ppm/ºC

Offset

±10ppm/ºC

Transfer A ccuracy2

±45ppm/ºC

Long Term

±0.1% /year @ +25ºC

POW ER SUPPLY

Requirements

+15V ±3%

20mA max

-15V ±3%

12mA max

+5V ±5%

105mA max

Rejection Ratio

0.05% /% (+15V ); 0.01% /% (-15V )

Power Consumption

1W max

TEM PERA TURE RA NGE

Specified

A DC541C/542C

0º to 70ºC

A DC541B/542B

-55ºC to +125ºC

Storage, A ll M odels

-65ºC to +150ºC

M ECHA NICA L

Case Style

Case A (ceramic): A DC542

Case Envelope Dimensions

Case B (metal): A DC541

PIN

FUNCTION

PIN

FUNCTION

1

BIPOLA R OFFSET

24

+10V INPUT

2

A NA LOG GND

23

+20V INPUT

3

SUM M ING JCT.

22

+15V

4

A NA LOG GND

21

–15V

5

BIT 1 (M SB)

20

–15V

6

BIT 2

19

BIT 8 (LSB)

7

BIT 3

18

BIT7

8

BIT 4

17

BIT6

9

BIT 1 (M SB)

16

BIT 5

10

STA TUS

15

+5V

11

DIGITA L GND

14

+5V

12

DIGITA L GND

13

STA RT

PIN

FUNCTION

PIN

FUNCTION

1

CLOCK OUT

24

+5V

2

DIGITA L GND

23

SRA RT

3

STA TUS

22

CLOCK IN

4

Bit 8 (LSB)

21

SERIA L OUT

5

Bit 7

20

–15V

6

Bit 6

19

15V

7

Bit 5

18

SUM M ING JCT

8

Bit 4

17

A NA LOG GND

9

Bit 3

16

BIPOLA R OFFSET

10

Bit 2

15

20V INPUT

11

Bit 1 (M SB)

14

10V INPUT

12

Bit 1 (M SB)

13

GA IN A DJUST

Consult factory for application information.

ADC541/542