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SN74LS181N 데이터시트(PDF) 5 Page - Motorola, Inc

부품명 SN74LS181N
상세설명  4-BIT ARITHMETIC LOGIC UNIT
PDF  9 Pages
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

SN74LS181N 데이터시트(HTML) 5 Page - Motorola, Inc

  SN74LS181N Datasheet HTML 1Page - Motorola, Inc SN74LS181N Datasheet HTML 2Page - Motorola, Inc SN74LS181N Datasheet HTML 3Page - Motorola, Inc SN74LS181N Datasheet HTML 4Page - Motorola, Inc SN74LS181N Datasheet HTML 5Page - Motorola, Inc SN74LS181N Datasheet HTML 6Page - Motorola, Inc SN74LS181N Datasheet HTML 7Page - Motorola, Inc SN74LS181N Datasheet HTML 8Page - Motorola, Inc SN74LS181N Datasheet HTML 9Page - Motorola, Inc  
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FAST AND LS TTL DATA
SN54/74LS181
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay,
(Cn to Cn+4)
18
13
27
20
ns
M = 0 V, (Sum or Diff Mode)
See Fig. 4 and Tables I and II
tPLH
tPHL
(Cn to F Outputs)
17
13
26
20
ns
M = 0 V, (Sum Mode)
See Fig. 4 and Table I
tPLH
tPHL
(A or B Inputs to G Output)
19
15
29
23
ns
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
tPLH
tPHL
(A or B Inputs to G Output)
21
21
32
32
ns
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
tPLH
tPHL
(A or B Inputs to P Output)
20
20
30
30
ns
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
tPLH
tPHL
(A or B Inputs to P Output)
20
22
30
33
ns
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
tPLH
tPHL
(AX or BX Inputs to FX Output)
21
13
32
20
ns
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
tPLH
tPHL
(AX or BX Inputs to FX Output)
21
21
32
32
ns
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
tPLH
tPHL
(AX or BX Inputs to FXH Outputs)
38
26
ns
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
tPLH
tPHL
(AX or BX Inputs to FXH Outputs)
38
38
ns
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
tPLH
tPHL
(A or B Inputs to F Outputs)
22
26
33
38
ns
M = 4.5 V (Logic Mode)
See Fig. 4 and Table III
tPLH
tPHL
(A or B Inputs to Cn+4 Output)
25
25
38
38
ns
M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V
(Sum Mode) See Fig. 6 and Table I
tPLH
tPHL
(A or B Inputs to Cn+4 Output)
27
27
41
41
ns
M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode)
tPLH
tPHL
(A or B Inputs to A = B Output)
33
41
50
62
ns
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
RL = 2.0 kΩ
(Diff Mode) See Fig. 5 and Table II
AC WAVEFORMS
Figure 5
Figure 6
Figure 4
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
INPUT
INPUT
A INPUT
B INPUT
tPLH
tPLH
tPLH
tPHL
tPHL
tPHL
OUTPUT
OUTPUT
OUTPUT



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