CMV1010YR datasheet(8/10 Pages) CALMIRCO

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CALIFORNIA MICRO DEVICES

CMV1010

Applications Information

1. Input Common Mode Range and Output

Voltage Considerations

The CMV1010 is capable of accommodating an input

common mode voltage equal to one volt below the

positive rail and all the way to the negative rail. It is

also capable of output voltages equal to both power

supply rails. Voltages that exceed the supply voltages

will not cause phase inversion of the output, however,

ESD diode clamps are provided at the inputs that can

be damaged if static currents in excess of ±5mA are

allowed to flow in them. This can occur when the

magnitude of input voltage exceeds the rail by more

than 0.3 volt. To preclude damage, an applications

resistor, R

S, in series with the input is recommended

as illustrated in Figure 1 whose value for R

S is given

by:

VIN – (V+ +0.3V)

S > —————————

5mA

For V+ (or V–) equal to 2.2 volts and V

IN equal to 10

volts, R

S should be chosen for a value of 2.5KΩ or

greater.

Figure 1.

2. Output Current and Power Dissipation

Considerations

The CMV1010 is capable of sinking and sourcing

output currents in excess of 7mA at voltages very

nearly equal to the rails. As such, it does not have any

internal short circuit protection (which would in any

event detract from its rail to rail capability). Although

the power dissipation and junction temperature rise are

small, a short analysis is worth investigating.

Obviously, the worst case from a power dissipation

point of view is when the output is shorted to either

ground in a single rail application or to the opposite

supply voltage in split rail applications. Since device

only draws 60

µA supply current (100µA maximum), its

contribution to the junction temperature, T

J, is negli-

gible. As an example, let us analyze a situation in

which the CMV1010 is operated from a 5 volt supply

and ground, the output is “programmed” to positive

saturation, and the output pin is indefinitely shorted to

ground. In general:

DISS = (V+ – VOUT)*IOUT + IS*V+

Where: P

DISS = Power dissipated by the chip

V+ = Supply voltage

OUT = The output voltage

S = Supply Current

The contribution to power dissipation due to supply

current is 200

µW and is indeed negligible as stated

above.

The primary contribution to power dissipation occurs in

the output stage. V+ – V

OUT would equal 5V – 0V = 5

V, and power dissipation would be equal to 35

µW.

J = TA + θJA* PDISS

Where: T

= The ambient temperature

JA = The thermal impedance of the package

junction to ambient

The SOT23 exhibits a

JA equal to 325°C/W. Thus for

our example the junction rise would be about 11.4

which is clearly not a destructive situation even under

an ambient temperature of 85°C.

3. Input Impedance Considerations

The CMV1010 exhibits an input impedance typically in

excess of 1 Tera

Ω (1 X 1012ohms) making it very

appropriate for applications involving high source

impedance such as photodiodes and high output

impedance transducers or long time constant integra-

tors. High source impedances usually dictate large

feedback resistors. But, the output capacitance of the

source in parallel with the input capacitance of the

CMV1010 (which is typically 3pF) create a parasitic

pole with the feedback resistor which erodes the

phase margin of the amplifier. The usual fix is to

bypass, R

F, as shown in Figure 2 with a small capaci-

tor to cancel the input pole. The usual formula for

calculating C

F always results in a value larger than that

is required:

—————— ± ——————

Π R

S CS

Π R

F CF

Since the parasitic capacitance can change between

the breadboard and the production printed circuit

board, we favor the use of a "gimmick", a technique

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