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SN54LS375 데이터시트(PDF) 3 Page - Motorola, Inc

부품명 SN54LS375
상세설명  4-BIT D LATCH
PDF  5 Pages
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

SN54LS375 데이터시트(HTML) 3 Page - Motorola, Inc

  SN54LS375 Datasheet HTML 1Page - Motorola, Inc SN54LS375 Datasheet HTML 2Page - Motorola, Inc SN54LS375 Datasheet HTML 3Page - Motorola, Inc SN54LS375 Datasheet HTML 4Page - Motorola, Inc SN54LS375 Datasheet HTML 5Page - Motorola, Inc  
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FAST AND LS TTL DATA
SN54/74LS375
Q (SN54LS/74LS375 ONLY)
DATA
ENABLE
TO OTHER LATCH
Q
LOGIC DIAGRAM
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Enable Pulse Width
20
ns
VCC = 5.0 V
ts
Setup Time
20
ns
VCC = 5.0 V
th
Hold Time
0
ns
CC = 5.0 V
D
E
Q
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tPLH
tPLH
tPLH
tPLH
tPHL
tPHL
tPHL
tPHL
ts
th
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.



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