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SST175 데이터시트(PDF) 2 Page - Calogic, LLC

부품명 SST175
상세설명  P-Channel JFET Switch
PDF  2 Pages
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제조업체  CALOGIC [Calogic, LLC]
홈페이지  http://www.calogic.net
Logo CALOGIC - Calogic, LLC

SST175 데이터시트(HTML) 2 Page - Calogic, LLC

  SST175 Datasheet HTML 1Page - Calogic, LLC SST175 Datasheet HTML 2Page - Calogic, LLC  
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CORPORATION
ELECTRICAL CHARACTERISTICS (TA = 25
oC unless otherwise specified)
SYMBOL PARAMETER
J174
J175
J176
J177
UNITS
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
IGSS
Gate Reverse
Current
(Note 1)
1111
nA
VDS = 0, VGS = 20V
VGS(off)
Gate Source
Cutoff Voltage
5
10
3
6
1
4
0.8
2.25
V
VDS = -15V, ID = -10nA
BVGSS
Gate Source
Breakdown
Voltage
30
30
30
30
VDS = 0, IG = 1
µA
IDSS
Drain
Saturation
Current
(Note 2)
-20
-135 -7
-70
-2
-35 -1.5
-20
mA
VDS = -15V, VGS = 0
ID(off)
Drain Cutoff
Current
(Note 1)
-1
-1
-1
-1
nA
VDS = -15V, VGS = 10V
rDS(on)
Drain-Source
ON Resistance
85
125
250
300
Ω
VGS = 0, VDS = -0.1V
Cdg(off)
Drain-Gate
OFF
Capacitance
5.5
5.5
5.5
5.5
pF
VDS = 0,
VGS = 10V
f = 1MHz (Note 3)
Csg(off)
Source-Gate
OFF
Capacitance
5.5
5.5
5.5
5.5
Cdg(on)
+ Csg(on)
Drain-Gate
Plus Source
Gate ON
Capacitance
32
32
32
32
VDS = VGS = 0
td(on)
Turn On Delay
Time
2
5
15
20
ns
Switching Time Test Conditions
(Note 3)
J174
J175
J176
J177
VDD
-10V
-6V
-6V
-6V
VGS(off)
12V
8V3V3V
RL
560
Ω
12k
Ω 5.6kΩ 10kΩ
VGS(on)
0V
0V
0V
0V
tr
Rise Time
5
102025
td(off)
Turn Off Delay
Time
5
101520
tf
Fall Time
10
20
20
25
NOTES: 1. Approximately doubles for every 10
oC increase in TA.
2. Pulse test duration -300
µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.



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