5-59

FAST AND LS TTL DATA

BCD TO 7-SEGMENT

DECODER

The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND

gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates

and one driver are connected in pairs to make BCD data and its complement

available to the seven decoding AND-OR-INVERT gates. The remaining

NAND gate and three input buffers provide lamp test, blanking input/ripple-

blanking input for the LS48.

The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on

the state of the auxiliary inputs, decodes this data to drive other components.

The relative positive logic output levels, as well as conditions required at the

auxiliary inputs, are shown in the truth tables.

The LS48 circuit incorporates automatic leading and / or trailing edge

zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any

time when the BI / RBO node is HIGH. Both devices contain an overriding

blanking input (BI) which can be used to control the lamp intensity by varying

the frequency and duty cycle of the BI input signal or to inhibit the outputs.

14

13

12

11

10

9

1

2

3

4

5

6

VCC

7

16

15

8

f

g

a

b

c

d

e

B

C

LT BI / RBO RBI

D

A

GND

CONNECTION DIAGRAM DIP (TOP VIEW)

LOGIC DIAGRAM

INPUT

BLANKING INPUT OR

RIPPLE-BLANKING

OUTPUT

RIPPLE-BLANKING

INPUT

LAMP-TEST

INPUT

A

B

C

D

a

b

c

d

e

f

g

OUTPUT

SN54/74LS48

BCD TO 7-SEGMENT

DECODER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXJ

Ceramic

SN74LSXXN

Plastic

SN74LSXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

7 1

2

6 3

5

13 12 11 10 9 15 14 4

A B C D LT RBI

a

b

c

d

e

f

g

BI/

RBO

SN54 / 74LS48