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74LS569 데이터시트(PDF) 3 Page - Motorola, Inc |
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74LS569 데이터시트(HTML) 3 Page - Motorola, Inc |
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3 / 8 page ![]() 5-575 FAST AND LS TTL DATA SN54/74LS569A DEFINITION OF FUNCTIONAL TERMS A, B, C, D The four programmable data inputs. CEP Count Enable Parallel. Can be used to enable and inhibit counting in high speed cascaded operation. CEP must be LOW to count. CET Count Enable Trickle. Enables the ripple carry output for cascaded operation. Must be LOW to count. CP Clock Pulse. All synchronous functions occur on the LOW-to-HIGH transition of the clock. LOAD Enables parallel load of counter outputs from data inputs on the next clock edge. Must be HIGH to count. U/D Up/Down Count Control. HIGH counts up and LOW counts down. ACLR Asynchronous Clear. Master reset of counters to zero when ACLR is LOW, independent of the clock. SCLR Synchronous clear of counters to zero on the next clock edge when SCLR is LOW. OE A HIGH on the output control sets the four counter outputs in the high impedance, and a LOW, enables the output. YA, YB, YC, YD The four counter outputs. RCO Ripple Carry Output. Output will be LOW on the maximum count on up-count. Upon down-count, RCO is LOW at 0000. CCO Clock Carry Output. While counting and RCO is LOW, CCO will follow the clock HIGH-LOW-HIGH transition. Note: Actual current flow direction shown DRIVING OUTPUT DRIVING OUTPUT DRIVEN INPUT VCC IOL IOH IOL IOH IIL IIH LOW-POWER SCHOTTKY INPUT/OUTPUT CURRENT INTERFACE CONDITIONS |
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