CAT28HT256

8-95

Advanced

Stock No. 21065-03 2/98

DEVICE OPERATION

Read

Data stored in the CAT28HT256 is transferred to the

data bus when

WE is held high, and both OE and CE are

held low. The data bus is set to a high impedance state

when either

CE or OE goes high. This 2-line control

architecture can be used to eliminate bus contention in

a system environment.

Byte Write

A write cycle is executed when both

CE and WE are low,

and

OE is high. Write cycles can be initiated using either

WE or CE, with the address input being latched on the

falling edge of

WE or CE, whichever occurs last. Data,

conversely, is latched on the rising edge of

WE or CE,

whichever occurs first. Once initiated, a byte write cycle

automatically erases the addressed byte and the new

data is written within 10 ms.

Figure 3. Read Cycle

ADDRESS

CE

OE

WE

tRC

DATA OUT

DATA VALID

DATA VALID

tCE

tOE

tOH

tAA

tOHZ

tHZ

VIH

HIGH-Z

tLZ

tOLZ

5096 FHD F04

1.3V

DEVICE

UNDER

TEST

1N914

3.3K

CL = 100 pF

OUT

CL INCLUDES JIG CAPACITANCE

Figure 2. A.C. Testing Load Circuit (example)

INPUT PULSE LEVELS

REFERENCE POINTS

2.0 V

0.8 V

2.4 V

0.45 V

5096 FHD F03

Note:

(1) Input rise and fall times (10% and 90%) < 10 ns.