9-93

CAT93CXXXX

Stock No. 21084-01 2/98

Advanced Information

Figure 6. EWEN/EWDS Instruction Timing

SK

CS

DI

STANDBY

10

0

*

* ENABLE=11

DISABLE=00

entered the self clocking mode. The ready/busy status

of the CAT93CXXXX can be determined by selecting

the device and polling the DO pin. Once cleared, the

contents of all memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busystatus

of the CAT93CXXXXcan be determined by selecting the

device and polling the DO pin. It is not necessary for all

memory locations to be cleared before the WRAL com-

mand is executed.

Erase/Write Enable and Disable

The CAT93CXXXX powers up in the write disable state.

Any writing after power-up or after an EWDS (write

disable) instruction must first be preceded by the EWEN

(write enable) instruction. Once the write instruction is

enabled, it will remain enabled until power to the device

is removed, or the EWDS instruction is sent. The EWDS

instruction can be used to disable all CAT93CXXXX

write and clear instructions, and will prevent any acci-

dental writing or clearing of the device. Data can be read

normally from the device regardless of the write enable/

disable status.

Erase All

Upon receiving an ERAL command, the CS (Chip Se-

The falling edge of CS will start the self clocking clear

cycle of all memory locations in the device. The clocking

of the SK pin is not necessary after the device has

Figure 7. ERAL Instruction Timing

SK

CS

DI

DO

STANDBY

tCS

HIGH-Z

HIGH-Z

10

1

BUSY

READY

STATUS VERIFY

tSV

tHZ

tEW

00