FEDL7029-04

ML7029

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(1): PCM data serial to parallel conversion output

(2): ADPCM data serial to parallel conversion output

A: (1) Data internal latch timing

B: (2) Data internal latch timing

Figure 8

In this device, internal operating timing is generated according to the SYNC signal (see Figure 8). Therefore, a

data slip may occur in the following timing when the PCM and ADPCM data is input.

1. When the PCM signal (PCMSI) is captured

If TS: PCM signal output (1) after serial/parallel conversion and A: internal latch timing in Figure 6 overlap, a

data slip occurs.

2. When the ADPCM signal (IR) is captured

If Tr: ADPCM signal output (2) after serial/parallel conversion and B: internal latch timing in Figure 7 overlap,

a data slip occurs.

The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay

into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1

s from

the timing A and B.

PCMSI

IS

Internal Clock Generation

ADPCM COD

S/P

A

SYNC

BCLK

(1)

PCMRO

IR

ADPCM DEC

P/S

Latch

B

(2)

Latch

S/P

P/S

Latch

Latch