RL78G13 datasheet(19/46 Pages) RENESAS

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RL78/G13

Serial Array Unit (UART Communication)

R01AN0459EJ0200

Rev. 2.00

Page 19 of 43

2014.03.24

Figure 5.8

UART0 Setup (2/3)

SCR00 register

 8297H

SDR00 register

 CE00H

NFEN0 register

 0001H

SIR01 register

 0007H

SMR01 register

 0122H

SAU channel 0 communication

operation setting

 Only perform transmission

 Phase with clock: type 1

 Error interrupt INTSREx

: Masked

 Output even parities

 Input/output in LSB first

 Stop bit length: 1 bit

 Data length: 8 bits

Channel 0 transfer clock

: Operation clock divided by 208

RxD3 pin noise filter

RxD2 pin noise filter

RxD1 pin noise filter

: OFF

RxD0 pin noise filter

: ON

Clear the error flag

SAU channel 1 operation mode

setting

 Channel 1 operation clock: CK00

 Channel 1 transfer clock

: Division of CK00

 Start trigger source

: Valid edge of the RxD pin

 Detect a falling edge as a start bit

 Channel 1 operation mode

: UART mode

 Channel 1 interrupt source

: Transfer end interrupt

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