RX64M datasheet(4/67 Pages) RENESAS

4 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 4 of 67

Feb 28, 2014

Interrupt

Interrupt controller

(ICUA)

 Peripheral function interrupts: 293 sources

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: 2 sources

 Non-maskable interrupts: 7 sources

 Sixteen levels specifiable for the order of priority

 Method of interrupt source selection:

The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128

vectors are selected from among the other 156 sources.)

External bus extension

 The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

 SDRAM interface connectable

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

DMA

DMA controller

(DMACAa)

 8 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

EXDMA controller

(EXDMACa)

 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

 Single-address transfer enabled with the EDACKn signal

 Activation sources: Software trigger, external DMA requests (EDREQn), and interrupt

requests from peripheral functions

Data transfer controller

(DTCa)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: External interrupts and interrupt requests from peripheral functions

I/O ports

Programmable I/O ports

 I/O ports for the 177-pin TFLGA (in planning), 176-pin LFBGA (in planning), and 176-pin

LQFP

I/O pins: 127

Input pin: 1

Pull-up resistors: 127

Open-drain outputs: 127

5-V tolerance: 19

 I/O ports for the 145-pin TFLGA (in planning) and 144-pin LQFP

I/O pins: 111

Input pin: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 18

 I/O ports for the 100-pin TFLGA (in planning) and 100-pin LQFP

I/O pins: 78

Input pin: 1

Pull-up resistors: 78

Open-drain outputs: 78

5-V tolerance: 17

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 119 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

Table 1.1

Outline of Specifications (3/9)

Classification

Module/Function

Description

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