L8401

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

2 of 5

www.unisonic.com.tw

QW-R123-018.a

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PIN CONFIGURATION

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FUNCTIONAL DIAGRAM

Fig.1

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FUNCTIONAL DESCRIPTION

The UTC L8401 includes one negative supply required for gate biasing from the single supply voltage, and all the

other bias requirements for external FETs.

A low current negative supply voltage includes an internal OSC and two 47nF external cap. The negative rail

generator is common to all devices. This negative supply voltage used to drive the FET’s gate to obtain the required

drain current because of he FET is a depletion mode transistor.

There are for stages in the IC to baising the four external FETS. The drain voltage of the external FET FET1~4 is

2.2 volts set by the UTC L8401.