CS22230 Mini PCI / USB Wireless Controller

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DS558PP1

Rev. 1.0

www.cirrus.com

2

Features

Embedded ARM Core and System Support Logic

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High Performance ARM7TDMI RISC processor core at 77MHz

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4KB integrated, one-way set associative, unified, write through cache

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Individual interrupt for each functional block

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Two 23-bit programmable (periodic or one-shot) general purpose timers

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8 Dword (32-bits) memory write and read buffers for high system performance

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Abort cycle detection and reporting for debugging

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ARM performance monitoring function for system fine-tuning

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Programmable performance improvement logic based on system configuration

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Flexible independent DMA engines for Mini PCI and Digital Radio functional units

Enhanced Memory Controller Unit

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Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM interface

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16-bit data bus with 12-bit address supporting up to 4MB at up to 103MHz SDRAM

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8-bit data bus with addressing support up to 1MB of boot ROM/Flash

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Programmable SDRAM timing and size parameters such as CAS latencies and number of banks

columns and rows

FEC codec

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High performance Reed-Solomon coding for error correction (255:239 block coding)

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Reduces symbol error probability of a typical 10e-3 error rate environment to 10e-9

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Programmable rate FEC engine to optimize channel efficiency

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Low latency, fully pipelined hardware encoding and decoding. Support byte wise single cycle

throughput up to 77MHz, with a sustain rate of 77MBps.

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Double buffering (64 Dword read/write buffer) to enhance system performance

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On the fly configuration of encoder and decoder

Digital Wireless Radio MAC

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Glue-less interface to 802.11b radio baseband transceiver

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11Mbps data rate

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32 Dword transmit/receive FIFO

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Supports clear channel assessment (CCA)

Power Management

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Host (Mini PCI) ACPI compliant

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Remote USB host wakeup

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Supports variable rate radio transmit, receive and standby radio power modes through two DACs

Clock and PLL Interface

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Single 44MHz crystal oscillator reference clock for Mini PCI version. 48MHz reference clock required

in USB option.

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Internal PLL to generate internal and on board clocks

USB Controller Interface

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12 Mbps USB 1.1 compliant device

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Supports 1 to 16 endpoints, endpoints can be bulk, isochronous or interrupt

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Variable endpoint buffer depths providing maximum flexibility for endpoint configurations

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Flexible configuration programming via EEPROM or firmware download

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Remote host wakeup