CS4220 CS4221

14

DS284PP3

5.1.6

CLOCKING ERROR (CLKE) (READ ONLY)

Default = 0

0 - No error

1 - Error

5.2

DAC Control (address 02h)

5.2.1

MUTE ON CONSECUTIVE ZEROS (MUTC)

Default = 0

0 - Disabled

1 - Enabled

Function:

The DAC output will mute following the reception of 512 consecutive audio samples of static 0 or -1

when this function is enabled. A single sample of non-static data will release the mute. Detection and

muting is done independently for each channel. The muting function is affected, similar to volume

control changes, by the SOFT bit in the DAC Control register.

5.2.2

MUTE CONTROL (MUTR-MUTL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The output for the selected DAC channel will be muted when this function is enabled. The muting

function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.

5.2.3

SOFT RAMP CONTROL (SOFT)

Default = 0

0 - Soft Ramp level changes

1 - Zero Cross level changes

Function:

Soft Ramp level changes will be implemented by incrementally ramping, in 0.5 dB steps, from the cur-

rent level to the new level. The rate of change defaults to 0.5 dB per 8 left/right clock periods and is

adjustable through the RMP bits in the DAC Control register.

Zero Cross level changes will be implemented in a single step from the current level to the new level.

The level change takes effect on a zero crossing to minimize audible artifacts. If the signal does not

encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods

(10.7 ms at 48 kHz sample rate). Zero crossing is independently monitored and implemented for each

channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level

change has occurred for the right and left channel.

765

4321

0

Reserved

MUTC

MUTR

MUTL

SOFT

Reserved

RMP1

RMP0

000

0000

0