CS4329

DS153F1

17

Digital Inputs

MCLK - Clock Input, PIN 8.

The frequency must be either 256×, 384× or 512× the input sample rate (Fs).

LRCK - Left/Right Clock, PIN 7.

This input determines which channel is currently being input on the Serial Data Input pin,

SDATA. The format of LRCK is controlled by DIF0, DIF1 and DIF2.

SCLK - Serial Bit Input Clock, PIN 9.

Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch

SDATA is controlled by DIF0, DIF1 and DIF2.

SDATA - Serial Data Input, PIN 10.

Two's complement MSB-first serial data of either 16, 18 or 20 bits is input on this pin. The

data is clocked into the CS4329 via the SCLK clock and the channel is determined by the

LRCK clock. The format for the previous two clocks is determined by the Digital Input Format

pins, DIF0, DIF1 and DIF2.

DIF0, DIF1, DIF2 - Digital Input Format, PINS 20, 19, 12

These three pins select one of seven formats for the incoming serial data stream. These pins set

the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in

Table 2.

DEM0, DEM1 - De-Emphasis Select, PINS 1, 2.

Controls the activation of the standard 50/15us de-emphasis filter for either 32, 44.1 or 48 kHz

sample rates.

AUTO-MUTE - Automatic Mute on Zero-Data, PIN 11.

When Auto-Mute is low the analog outputs are muted following 8192 consecutive LRCK

cycles of static 0 or 1 data. Mute is canceled with the return of non-static input data.

MUTE_R , MUTE_L Mute, PINS 15, 16.

MUTE_L low activates a muting function for the Left channel. MUTE_R low activates a

muting function for the Right channel.