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CS4331 데이터시트(PDF) 11 Page - Cirrus Logic |
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CS4331 데이터시트(HTML) 11 Page - Cirrus Logic |
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11 / 38 page ![]() LRCK SCLK Left Channel Right Channel SDATA 6543 210 987 15 14 13 12 11 10 65432 10 987 15 14 13 12 11 10 Internal SCLK Mode External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK INT SCLK = 32 Fs if MCLK/LRCK = 512 or 256 INT SCLK = 48 Fs if MCLK/LRCK = 384 Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 32 cycles per LRCK Figure 7. CS4333 SCLK Data Format LRCK SCLK Left Channel Right Channel SDATA 654 3210 987 15 14 13 12 11 10 17 16 6543 210 987 15 14 13 12 11 10 17 16 External SCLK Mode I 2S, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 36 cycles per LRCK Figure 6. CS4331 External SCLK Data Format (I 2S) CS4330, CS4331, CS4333 DS136F1 11 |
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