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CS43L41 데이터시트(PDF) 31 Page - Cirrus Logic

부품명 CS43L41
상세설명  Low Power 24-Bit, 96 kHz DAC with Volume Control?
PDF  36 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L41 데이터시트(HTML) 31 Page - Cirrus Logic

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CS43L41
DS473PP1
31
LRCK
SCLK
Left Channel
SDATA
6543
210
7
23 22 21 20 19 18
6
543
210
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 24-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 48 Cycles per LRCK
Period
Figure 23. CS43L41 Format 3
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5432
10
98
7
15 14 13 12 11 10
10
65
432
10
98
7
15 14 13 12 11 10
17 16
17 16
32 clocks
19 18
19 18
Internal SCLK Mode
External SCLK Mode
Right Justified, 20-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 20-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 40 Cycles per LRCK
Period
Figure 24. CS43L41 Format 4
LRCK
SCLK
Left Channel
Right Channel
SDATA
6543
210
98
7
15 14 13 12 11 10
6
543
210
98
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit DataINT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 16-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 32 Cycles per LRCK
Period
Figure 25. CS43L41 Format 5



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