CS43L43

30

DS479PP3

GND, Logic “1” = VL.)

Notes: 5. This serial clock is required only in Control Port Mode when the MCLK Divide bit is enabled.

Parameters

Symbol

Min

Max

Units

External SCLK Mode

MCLK Frequency

1.024

51.2

MHz

MCLK Duty Cycle

45

55

%

Input Sample Rate

Single-Speed Mode

Double-Speed Mode

Fs

Fs

2

50

50

100

kHz

kHz

LRCK Duty Cycle

40

60

%

SCLK Pulse Width Low

20

-

ns

SCLK Pulse Width High

20

-

ns

SCLK Period

-s

SCLK Frequency

-

Hz

SCLK Frequency

(Note 10)

-

Hz

SCLK rising to LRCK edge delay

20

-

ns

SCLK rising to LRCK edge setup time

20

-

ns

SDATA valid to SCLK rising setup time

20

-

ns

SCLK rising to SDATA hold time

20

-

ns

2

MCLK

------------------

MCLK

2

------------------

MCLK

4

------------------

sclkh

t

slrs

t

slrd

t

sdlrs

t

sd h

t

sclkl

t

SD AT A

SC LK

LR C K

Figure 19. External Se-

rial Mode Input Timing