CS5126 datasheet(29/32 Pages) CIRRUS

29 / 32 page

Miscellaneous Hints on Using the Evaluation

Board

Always hit the reset button after powering-up the

board. The CS5126 is self calibrating and require

the reset signal to initiate the calibration proce-

dure.

P4 controls the ADC input mux. This is used to

set the mux to be continuously connected to one

channel, or to be toggling between two channels.

This is very useful for evaluating oversampled

vs. regular sampling digital audio.

P10 controls the Data Ready pulses from the on-

board logic. To cause every data sample to be

read, select option 0. If you wish to read only

every alternate sample, then select option 1 or 2,

depending on whether you wish to read every left

channel value, or every right channel value. This

is useful for evaluating the part with a test system

which does not separate alternate values.

CDBCAPTURE Interface

Figure 8 illustrates the CDBCAPTURE interface

that can be constructed in the digital patch area.

A 2-row, 10 pin stake header is wired as shown.

GND

(GND-Digital Patch)

+5V

FRAME

SCLK

SDATA

(+5VL - Digital Patch)

GND

(DRDY - P8)

(SCLK - U9-11)

(SDATA - U8-14)

Circuit Board

(Top View)

Figure 8. CDBCAPTURE Header Signal Pattern

CDB5126

DS32DB5

CS5126 데이터시트(PDF) 29 Page - Cirrus Logic