CS4923-CL datasheet(36/56 Pages) CIRRUS

36 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

6.2.2 Motorola Parallel Host Mode

Motorola parallel host mode is accomplished with

CS, DS, R/W, A[1:0], and DATA[7:0]. Table 6

shows the pin name, pin description and pin

number of each signal on the CS4923/4/5/6/7/8/9.

In Motorola host interface mode, the host interface

pins act as an active-low chip select, CS, an active-

low data strobe, DS, and a R/W control signal.

Internally to the CS492X, DS and CS are logically

ANDED. Therefore, in some cases, DS and CS can

be externally tied together with a common active-

low strobe. Otherwise, in long decoder delay

scenarios, read or write cycles can be terminated

earlier by connecting the microprocessor active-

low data-strobe signal to the CS492X DS and a

delayed final active-low chip select independently

to the CS pin.

When the DSP writes a byte to the HOSTMSG

read. During read cycles, DATA[7:0] are driven

when R/W is high and DS and CS are both low.

DATA[7:0] are released with the earliest of CS or

DS going high. The HOUTRDY bit of the

CONTROL register is cleared after the host reads

from the HOSTMSG register.

Write cycles occur with R/W low followed by DS

and CS both going low. The A[1:0] address pins

select the specific address of the register to be

written and DATA[7:0] carry the data to be written.

For write cycles, the first of CS and DS going high

latches data. Data must be held sufficiently to

satisfy the hold time as given in the timing section.

The HINBSY is set when the host writes the

HOSTMSG register. This bit is cleared when the

byte in the HOSTMSG is internally read by the

DSP.

6.3 SPI Serial Host Interface

For SPI communications, the CS4923/4/5/6/7/8/9

always acts as a slave. Serial SPI communication

with the CS4923/4/5/6/7/8/9 is accomplished with

5 communication lines: CS, SCCLK, SCDIN,

SCDOUT and INTREQ. Table 7 shows the pin

name, pin description and pin number of each

signal on the CS4923/4/5/6/7/8/9. CS is an active

low chip select and must be held low for writes to

and reads from the part. SCCLK is an input to the

CS492X that clocks data in and out of the device on

its rising edge. SCDIN is the data input and should

be valid on the rising edge of SCCLK. SCDOUT is

the data output and will be valid on the rising edge

of SCCLK. INTREQ is an open drain, active-low

interrupt request signal that is driven low by the

CS492X when there is data to be read out.

Pin Name

Pin Description

Pin Number

Chip Select

Data Strobe

R/W

Read or Write Enable

INTREQ

Interrupt Request

DATA7

Data Bit 7

DATA6

Data Bit 6

DATA5

Data Bit 5

DATA4

Data Bit 4

DATA3

Data Bit 3

DATA2

Data Bit 2

DATA1

Data Bit 1

DATA0

Data Bit 0

Table 6. Motorola Parallel Host Mode Pin Assignments

Pin Name

Pin Description

Pin Number

Chip Select

SCDIN

Serial Data Input

SCCLK

Serial Control Clock

SCDOUT

Serial Data Output

INTREQ

Interrupt Request

Table 7. SPI Serial Mode Pin Assignments

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