CS5181

6

DS250PP1

AGND = DGND = 0 V; MODE = VD+)

Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.

11. RESET, SYNC, and PWDN have Schmitt-trigger inputs.

12. Specifications applicable to complementary signals SCLK and SDO.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 2)

MCLK

0.512

25 to 40

41

MHz

Master Clock Duty Cycle

45

-

55

%

Rise Times

(Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

-

-

-

-

-

20

100

.2/MCLK

-

ns

s

ns

Fall Times

(Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

-

-

-

-

-

20

100

.2/MCLK

-

ns

s

ns

Calibration/Sync

RESET rising to MCLK rising

-3

-

ns

RESET rising recognized, to FSO falling

-

988205/MCLK

-

s

SYNC rising to MCLK rising

-

3

-

ns

SYNC rising recognized to FSO falling

-

5161/MCLK

-

s

PWDN rising recognized to FSO falling

-

5168/MCLK

-

s

SYNC high time

1/MCLK

-

-

s

RESET low time

1/MCLK

-

-

s

Serial Port Timing

(Note 12)

SCLK frequency

-

MCLK/3

-

Hz

SCLK high time

-1/MCLK

-

s

SCLK low time

-2/MCLK

-

s

FSO falling to SCLK rising

-2/MCLK + 2E-9

-

s

SCLK falling to new data bit

-1.5

-

ns

SCLK rising to FSO rising

-1/MCLK - 2E-9

-

s

FSO

SCLK

SDATA XX

MSB

MSB-1

LSB-1

LSB

XX

t

1

t

2

t

3

t

4

t

5

Figure 1. Serial Port Timing (not to scale)