CS5360

16

DS280PP2

5. PIN DESCRIPTIONS

High Pass Filter Defeat - HP DEFEAT

Pin 1, Input

Function

A high logic level on this pin disables the digital high pass filter. A low logic level on this pin enables the

high pass filter.

Overflow - OVFL

Pin 2, Input

Function

Overflow indicates analog input overrange, for both the Left and Right channels, since the last update

request on the PEAK UPDATE (PU) pin. A value of 1 in the register indicates an overrange condition.

The left channel information is output on OVFL during the left channel portion of LRCK. The right

channel information is available on OVFL during the right channel portion of LRCK. The registers are

updated with a high to low transition on the PEAK UPDATE pin. A 47 k

Ω pull-down resistor on this pin

will set the CS5360 in Master Mode.

Positive Analog Power - VA+

Pin 3, Input

Function:

Positive analog supply. Nominally +5 volts.

Analog Ground - AGND

Pin 4, Input

Function:

Analog ground reference.

DGND - Digital Ground

Pin 5, Input

Function:

Digital ground reference.

1

2

3

4

5

6

7

813

14

15

16

17

18

19

20

DIF0

DIF1

RST

AINL+

AINL-

CMOUT

AINR-

AINR+

SCLK

MCLK

VD+

DGND

AGND

VA+

OVFL

HPDEFEAT

9

10

11

12

LRCK

PU

FRAME

SDATA

Serial Data Clock

Master Clock

Digital Power

Digital Ground

Analog Ground

Analog Power

Overflow

High Pass Filter Defeat

Frame Signal

Serial Data Output

Digital Interface Format 0

Digital Interface Format 1

Reset

Non-Inverting Left Channel Input

Inverting Left Channel Input

Common Mode Output

Inverting Right Channel Input

Non-Inverting Right Channel Input

Left / Right Clock

Peak Update