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W150
PRELIMINARY
13
Document #: 38-00857-A
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz (24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for de-
termining series termination value.
25
Ω
Ordering Information
Ordering Code
Package
Name
Package Type
W150
H
56-Pin SSOP (300-mil)
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