ICS571

LOW PHASE NOISE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER

2

ICS571

REV H 051310

Pin Assignment

Feedback Configuration Table and Frequency Ranges (at 3.3 V)

Pin Descriptions

Key: CI = clock input; I = input; O = output; P = power supply connection.

Feedback From

CLK

CLK/2

Input Range

CLK

Input clock frequency

Input clock frequency/2

20 to 160 MHz

CLK/2

2x Input clock frequency

Input clock frequency

10 to 80 MHz

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

ICLK

CI

Reference clock input.

2

VDD

P

Connect to +3.3 V or +5 V. Must be same as other VDD.

3

GND

P

Connect to ground.

4

CLK/2

O

Clock output per table above. Low skew divide by two of pin 7 clock.

5

GND

P

Connect to ground.

6

VDD

P

Connect to +3.3 V or +5 V. Must be same as other VDD.

7

CLK

O

Clock output per table above.

8

FBIN

CI

Feedback clock input. Connect to CLK or CLK/2 per table above.