ICS810251I Data Sheet

VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR

ICS810251AGI REVISION B OCTOBER 5, 2012

9

©2012 Integrated Device Technology, Inc.

Schematic Example

Figure 1 shows an example of the 810251I application schematic. In

decoupling capacitors should be located as close as possible to the

power pin. The input is driven by an LVCMOS driver. An optional

3-pole filter can also be used for additional spur reduction. It is

recommended that the loop filter components be laid out for the

3-pole option. This will also allow the 2-pole filter to be used.

Figure 1. P.C. ICS810251I Schematic Example

Cp

0.001 uF

LF1

RD1

Not Install

RU1

1K

Logic Control Input Examples

VDD

Cp

TBD

To Logic

Input

pins

Zo = 50

R3

TBD

Set Logic

Input to

'1'

Cs

TBD

R2

10

LF0

VDD

VDDO

VDD

C30

0.01u

LVCMOS_Receiv er

R1

33

Rs

TBD

VDD

Q1

LVCMOS_Driv er

XTAL_IN

C2

0.1u

Set Logic

Input to

'0'

X2

C6

SPARE

XTAL_OUT

To Logic

Input

pins

C5

SPARE

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

PLL_SEL

GND

Reserv ed

Q

VDDO

OE

VDDA

VDD

GND

XTAL_OUT

XTAL_IN

GND

LF0

LF1

VDD

CLK_IN

C4

0.1u

3-pole loop filter example - (optional)

C3

TBD

Cs

10uF

C1

0.1u

VDDA

Rs

1K

VDD

VDD=VDDO=3.3V

RD2

1K

Zo = 50

C45

10u

R4

33

RU2

Not Install

2-pole loop filter