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DS2180A 데이터시트(PDF) 13 Page - Dallas Semiconductor |
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DS2180A 데이터시트(HTML) 13 Page - Dallas Semiconductor |
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13 / 35 page ![]() DS2180A 13 of 35 TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11 NOTES: 1. TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated for insertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is sampled during even frames. 2. If TCR.5=1, TSER is sampled during the F-bit time of CRC frames for insertion into the outgoing data stream (193E framing only). |
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