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Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Features

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

Design Security Feature

Cyclone III LS devices offer the following design security features:

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Configuration security using advanced encryption standard (AES) with 256-bit

volatile key

■

software

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Design separation flow achieves both physical and functional isolation

between design partitions

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Ability to disable external JTAG port

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Error Detection (ED) Cycle Indicator to core

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Provides a pass or fail indicator at every ED cycle

■

Provides visibility over intentional or unintentional change of configuration

random access memory (CRAM) bits

■

Ability to perform zeroization to clear contents of the FPGA logic, CRAM,

embedded memory, and AES key

■

Internal oscillator enables system monitor and health check capabilities

Increased System Integration

■

High memory-to-logic and multiplier-to-logic ratio

■

High I/O count, low-and mid-range density devices for user I/O constrained

applications

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Adjustable I/O slew rates to improve signal integrity

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Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,

LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS

■

Supports the multi-value on-chip termination (OCT) calibration feature to

eliminate variations over process, voltage, and temperature (PVT)

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Four phase-locked loops (PLLs) per device provide robust clock management and

synthesis for device clock management, external system clock management, and

I/O interfaces

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Five outputs per PLL

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Cascadable to save I/Os, ease PCB routing, and reduce jitter

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Dynamically reconfigurable to change phase shift, frequency multiplication or

division, or both, and input frequency in the system without reconfiguring the

device

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Remote system upgrade without the aid of an external controller

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Dedicated cyclical redundancy code checker circuitry to detect single-event upset

(SEU) issues

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custom-fit embedded processing solutions