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74LVC86APW 데이터시트(PDF) 2 Page - List of Unclassifed Manufacturers

부품명 74LVC86APW
상세설명  Quad 2-input EXCLUSIVE-OR gate
PDF  15 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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74LVC86APW 데이터시트(HTML) 2 Page - List of Unclassifed Manufacturers

  74LVC86APW Datasheet HTML 1Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 2Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 3Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 4Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 5Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 6Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 7Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 8Page - List of Unclassifed Manufacturers 74LVC86APW Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
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74LVC86A_5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 05.00 — 15 May 2006
2 of 15
Philips Semiconductors
74LVC86A
Quad 2-input EXCLUSIVE-OR gate
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
mna787
1A
1B
1Y
2
1
3
2A
2B
2Y
5
4
6
3A
3B
3Y
10
9
8
4A
4B
4Y
13
12
11
mna786
3
=1
=1
=1
=1
2
1
6
5
4
8
10
9
11
13
12
Fig 3.
Logic diagram for one gate
mna788
Y
A
B
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4.
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
86
1A
VCC
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
001aad103
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aad105
86
Transparent top view
2Y
3A
2B
3B
2A
4Y
1Y
4A
4B
1B
GND(1)
6
9
5
10
4
11
3
12
2
13
terminal 1
index area



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