ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

18 of 25

nCS

Figure 10: Internal Clock Mode Timing with interleaved Control Byte transmission

Table 5: Control Byte Format

BIT

Name

Description

7

(MSB)

START

The Start Bit is defined by the first logic ‘1’ after nCS goes low.

6

5

4

A2

A1

A0

Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer.

For further details on the decoding see also Table 3 and Table 4.

3

UNI/BIP

Output Code Bit. The value of the bit determines conversion mode and output code format.

‘1’

=

unipolar - straight binary coding

‘0’

=

bipolar - two’s complement coding

2

SGL/DIF

Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit

controls the setting of the input multiplexer

‘1’

=

single ended - all channels CH0 … CH7 measured referenced to COM

‘0’

=

differential - the voltage between two channels is measured

1

0 (LSB)

PD1

PD0

Power Down and Clock Mode Select Bits

PD1

PD0

Mode

0

0

Full Power-Down

0

1

Fast Power-Down

1

0

Internal clock mode

1

1

External clock mode

S

BIP

SGL/

DIF

PD1 PD0

B11 B10 B9

B2 B1 B0

Zero filled

Acquire

Idle

Conversion

(MSB)

(LSB)

1

8

(Start)

nCS

SCLK

DIN

SSTRB

DOUT

B5

B4

B3

B8 B8 B6

1

8

1

8

S

BIP

SGL/

DIF

PD1 PD0

Acquire

Result Output

S

BIP

SGL/

DIF

PD1 PD0

SCLK

1

8

1

8

1

8

DIN

(Start)

Acquire

Idle

Conversion

Idle

SSTRB

B11 B10

Zero filled

B9 B8 B7 B6 B5

B4

B3 B2 B1 B0

DOUT

(MSB)

(LSB)