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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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EP5357LUI 데이터시트(PDF) 14 Page - Altera Corporation |
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EP5357LUI 데이터시트(HTML) 14 Page - Altera Corporation |
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14 / 19 page  EP5357LUI/EP5357HUI EP5357LUI External Voltage Divider The external divider option is chosen by connecting VID pins VS2-VS0 to VIN or a logic “1” or “high”. The EP5357LUI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 11. The output voltage is selected by the following formula: ( ) Rb Ra OUT V V + = 1 6 . 0 Ra must be chosen as 237K Ω to maintain loop gain. Then Rb is given as: Ω − = 6 . 0 10 2 . 142 3 OUT b V x R VOUT can be programmed over the range of 0.6V to (VIN – 0.25V). NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider. NOTE: LLM is not functional when using the external divider option. Tie the LLM pin to AGND. VIN VSense VS0 VS2 10 µF 4.7uF VOUT VOUT AGND ENABLE Ra Rb VFB VS1 PGND AVIN PVIN Figure 11: EP5357LUI using external divider EP5357HUI High VID Range Programming The EP5357HUI VOUT settings are optimized for higher nominal voltages such as those required to power IO, RF, or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) preset output voltage settings. The EP5357HUI does not have an external divider option. As with the EP5357LUI, the VID pin settings can be changed while the device is enabled. Table 3 shows the VS0-VS2 pin logic states for the EP5357HUI and the associated output voltage levels. A logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. These pins must not be left floating. Table 3: EP5357HUI VID Voltage Select Settings Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements . Pre-Bias Start-up The EP5357xUI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EP5357xUI is not pre-biased when the EP5357xUI is first enabled. Input Filter Capacitor For ILOAD ≤ 500mA, CIN = 2.2uF For ILOAD > 500mA CIN = 4.7uF. 0402 capacitor case size is acceptable. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with VS2 VS1 VS0 VOUT 0 0 0 3.3 0 0 1 3.0 0 1 0 2.9 0 1 1 2.6 1 0 0 2.5 1 0 1 2.2 1 1 0 2.1 1 1 1 1.8 14 www.altera.com/enpirion 03409 October 11, 2013 Rev E |
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